This disclosure relates to data processing and storage, and more specifically, to management of a data storage system, such as a flash memory system, to promote storage system endurance through wear leveling.
NAND flash memory is an electrically programmable and erasable non-volatile memory technology that stores one or more bits of data per memory cell as a charge on the floating gate of a transistor. In a typical implementation, a NAND flash memory array is organized in blocks (also referred to as “erase blocks”) of physical memory, each of which includes multiple physical pages each in turn containing a multiplicity of memory cells. By virtue of the arrangement of the word and bit lines utilized to access memory cells, flash memory arrays can generally be programmed on a page basis, but are erased on a block basis.
As is known in the art, blocks of NAND flash memory must be erased prior to being programmed with new data. A block of NAND flash memory cells is erased by applying a high positive erase voltage pulse to the p-well bulk area of the selected block and by biasing to ground all of the word lines of the memory cells to be erased. Application of the erase pulse promotes tunneling of electrons off of the floating gates of the memory cells biased to ground to give them a net positive charge and thus transition the voltage thresholds of the memory cells toward the erased state. Each erase pulse is generally followed by an erase verify operation that reads the erase block to determine whether the erase operation was successful, for example, by verifying that less than a threshold number of memory cells in the erase block have been unsuccessfully erased. In general, erase pulses continue to be applied to the erase block until the erase verify operation succeeds or until a predetermined number of erase pulses have been used (i.e., the erase pulse budget is exhausted).
A NAND flash memory cell can be programmed by applying a positive high program voltage to the word line of the memory cell to be programmed and by applying an intermediate pass voltage to the memory cells in the same string in which programming is to be inhibited. Application of the program voltage causes tunneling of electrons onto the floating gate to change its state from an initial erased state to a programmed state having a net negative charge. Following programming, the programmed page is typically read in a read verify operation to ensure that the program operation was successful, for example, by verifying that less than a threshold number of memory cells in the programmed page contain bit errors. In general, program and read verify operations are applied to the page until the read verify operation succeeds or until a predetermined number of programming pulses have been used (i.e., the program pulse budget is exhausted).
Over time, the high voltages applied during the program and erase operations tend to degrade the gate oxide of the floating gates of the transistors forming the memory cells of the blocks. This damage to the memory cells, often referred to as “wear,” limits the useful lifetime (or “endurance”) of blocks of NAND flash memory, where endurance is typically expressed as the number of program/erase (P/E) cycles for which a block can be utilized prior to the number of errors occurring in the block reaching the level that the block is no longer useful for storing data. Given the limited endurance of the various blocks of flash memory comprising a data storage system, one function of flash controllers is to maximize the useful lifetime of the overall data storage system by extending the endurance of the constituent blocks.
Among the techniques flash controllers commonly employ to extend endurance of flash-based data storage systems is wear leveling. Wear leveling attempts to equalize the wear of the blocks across a data storage system. Various prior art wear leveling techniques have experienced various levels of success in equalizing wear.